Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may include non-volatile memory (for example, flash memory) and volatile memory (for example, volatile SRAM memory) implemented in a single integrated circuit. Flash memory cells of the PLD may be programmed with configuration data to be downloaded into volatile SRAM cells to determine the user-defined functionality of the PLD.
The flash memory cells typically require programming voltages in a range of approximately 9.5 V to 10 V. Such programming voltages are substantially higher than typical operating voltages of volatile memory or other logic transistors of the PLD which may, for example, operate in a range of approximately 1.2 V to 3.3 V. As a result, PLDs may further include high voltage transistors to accommodate flash memory cell programming voltages.
However, in advanced integrated circuits having feature sizes of approximately 130 nm and smaller, individual high voltage transistors may be unable to sustain the voltages required for programming flash memory cells. In particular, high voltage transistors in such implementations may exhibit a relatively low breakdown voltage (for example, in the range of approximately 5 V to 8 V). As a result, the high voltage transistors may be implemented in a cascode configuration, with the programming voltages being distributed across a plurality of high voltage transistors (for example, a 10 V programming voltage with 5 V distributed across two high voltage transistors).
Unfortunately, cascoded high voltage transistors typically occupy a large die area. Consequently, the peripheral circuitry required to program a flash memory cell array in such implementations can be significantly larger than the flash memory cell array itself. This disparity can result in a very low array efficiency in the PLD.
The low breakdown voltage exhibited by certain high voltage transistors can be attributed to abrupt junctions between lightly doped drain (LDD) regions and channels of the high voltage transistors. These abrupt junctions are caused by tight thermal budget requirements imposed by conventional manufacturing processes for integrated circuits having flash memory cells, high voltage transistors, and low voltage transistors on a shared die. Typically, the shallower source/drain regions of low voltage transistors cannot sustain the high temperatures applied in annealing operations used in the formation of flash memory cells. As a result, flash memory cells are typically formed first, followed by the simultaneous formation of the high and low voltage transistors.
In this regard, a stacked gate structure of the flash memory cell may be formed, followed by implantation of source/drain regions of the flash memory cell. Thermal annealing is then performed to oxidize sidewalls of the stacked gate structure at temperatures of approximately 900 degrees C. Thereafter, gates of the high voltage and low voltage transistors may be etched, and LDD regions of the high and low voltage transistors may be implanted, causing abrupt junctions to be formed between the LDD regions and channels of the transistors. As previously explained, the abrupt junctions formed in the high voltage transistors can result in a low breakdown voltage which necessitates the use of plural high voltage transistors in a cascode configuration to support programming voltages of the flash memory cells.
In view of the foregoing, there is a need for an improved approach to the formation of high voltage transistors that may individually support appropriate programming voltages of flash memory cells on a shared die without requiring cascoding of the high voltage transistors. In addition, there is a need to provide such transistors while still permitting the formation of low voltage logic transistors on the shared die.